Integrated circuits (“ICs”) vary in complexity from, for example, an analog circuit comprising a few basic electronic components, such as transistors and diodes, to a complex digital system including hundreds of millions of transistors. Although different design methods and Electronic Design Automation (“EDA”) tools are arranged to design ICs of various levels of complexity, the fundamental process of IC design remains unchanged. That is, IC design engineers design an integrated circuit by transforming a circuit specification into geometric descriptions of physical components that in combination form the basic electronic components. In general, the geometric descriptions are polygons of various dimensions, representing conductive features located in different processing layers. The detailed geometric descriptions of physical components are generally referred to as integrated circuit layouts. After the creation of an initial integrated circuit layout, the integrated circuit layout is usually tested and optimized through a set of steps in order to verify that the integrated circuit meets the design specification and will perform as desired.
In a typical post-design testing and optimization step, after an integrated circuit design process is completed, an initial integrated circuit layout is created. The layout is first checked against design rules and then verified to be equivalent to the desired design schematic. This step is generally referred to as Design-Rule Check (DRC) and Layout Versus Schematic (LVS).
A step of RC extraction is subsequently performed in order to “extract” electrical characteristics of the layout. The common electrical characteristics that are extracted from an integrated circuit layout include capacitance and resistance in the electronic devices and on the various interconnects (also generally referred to as “nets”) that electrically connect the aforementioned devices. This step is also referred to as “parasitic extraction” because these capacitance and resistance values are not intended by the designer but rather result from the underlying device physics of the device configurations and materials used to fabricate the IC.
The designed IC is then simulated to insure the design meets the specification with the parasitic capacitance and resistance in the IC. If the parasitic capacitance and resistance cause undesirable performance, the integrated circuit layout is typically changed through one or more design optimization cycles. If the simulation results satisfy the design specification, the design process is completed.
It is known that the parasitic capacitance and resistance can cause various detrimental effects in a designed IC, such as undesired long signal delays on the nets. Thus, the impact of the parasitic capacitance and resistance on the performance of the designed IC must be accurately predicted so that design engineers can compensate for these detrimental effects through proper design optimization steps.
It is also recognized that, when device feature sizes shrink down to the ultra-deep submicron range (less than 0.25 micron), interconnect delays begin to dominate the total delay in an IC. Moreover, when FinFET technology is used, the parasitic capacitance between gate electrodes and semiconductor fins also plays an important role in the parasitic capacitance in additional to the parasitic capacitance between gate electrodes and metal contacts. Existing EDA tools, however, are not designed to handle the complex parasitic in the FinFETs.